Lead and grow the centralized IP Integration Digital team; define strategy and requirements; oversee transistor-level design, characterization, Verilog modeling, Cadence-based simulation and layout; collaborate with product, foundry, and quality teams to deliver qualified digital and I/O IP on schedule.
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
This high visibility role is responsible for managing the centralized IP Integration Digital team. In this position, you will work directly with product design leadership to set strategy, define requirements, and execute to schedules. Requires collaboration with product PMs and design managers to ensure the team delivers IP on time with high quality for in-flight programs.
The team is responsible for the characterization, and verification of 3rd party IP, as well as custom IP such as OTP, NVM, custom IO and a multitude of custom de-glitch cells, delay macros, along with dynamic and static level shifters. This includes transistor-level design of the custom IP, characterization for timing, working with layout teams to get the IP on silicon, working with design teams to define the specs for the IP, developing Verilog models for the IP, and providing guidance for integration of the IP into the chip level floorplan.
Responsibilities:
- Manage, mentor & grow the IP integration team.
- Lead team in the design, simulation, and optimization of Digital IP circuits.
- Deliver characterization and modeling of Digital IP and I/O libraries to support mixed-signal design flow.
- Put flows and methodology in place to develop, release and maintain Digital IP and I/O libraries and models.
- Collaborate with foundry teams on development and release of 3rd party IP.
- Work closely with quality teams to make sure IP meets qualification requirements along with communications of these requirements to foundries, vendors and customers.
Required Skills and Qualifications:
- This position requires 10+ years of proven experience leading engineering teams.
- Requires a Master's degree in Electrical Engineering or a closely related field.
- Good understanding of transistor-level circuit simulation and design.
- Understand power and speed tradeoffs in the design of Digital IPs.
- Help in the design of low leakage IP’s to be used in mobile phone and IoT applications.
- Must understand layout and be able to guide layout engineers.
- Proficiency with Cadence schematic capture, layout, and simulation tools.
- Effective oral and written communication is a must.
#LI-Hybrid
#LI-TM1
At Cirrus Logic, we believe that diversity drives innovation, and we are committed to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued. We aim to promote a workplace where everyone can contribute irrespective of race, colour, national origin, religion or belief, gender or gender identity, sexual orientation, age, marital status, pregnancy status, or disability.
Top Skills
Cadence
Layout
Mixed-Signal Design Flow
Schematic Capture
Transistor-Level Circuit Simulation
Verilog
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