The Senior Physical Design Engineer will implement RTL to GDS2 physical designs for ASIC projects, collaborate with design teams, and enhance methodologies.
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career!
We have an exciting opportunity for a talented Senior Physical Design Engineer to join our growing team in Edinburgh. In this role, you will have the opportunity to implement industry leading mixed-signal SOCs for consumer markets and become part of an organisation operating at the forefront of cutting-edge technology. This role would suit a candidate with an ability to work independently and as part of a wider design team.
Responsibilities:
- All aspects of RTL to GDS2 physical implementation for complex ASIC projects.
- Working with Digital Design, Analogue Layout and DFT teams to ensure on time and high-quality results.
- Participating in project scoping and planning activities.
- Developing P&R methodologies for continuous improvement.
Required Skills and Qualifications:
- Bachelor's, Master’s or PhD degree in Electrical Engineering or related discipline and proven industry experience in a Physical Design position.
- Wide experience with industry standard EDA tools for digital implementation and signoff, and the ideal candidate should be familiar with:
- Synopsys Design Compiler and Primetime
- Cadence Innovus, Voltus and Conformal
- Hands-on working knowledge of deep sub-micron ASIC implementation and expertise in areas such as:
- RTL synthesis
- Timing constraint debug and development
- Floorplanning and power planning
- Clock tree synthesis
- P&R optimisation, timing closure and ECO implementation
- Static timing analysis
- Logical Equivalence Checks
- Power and EMIR analysis
- Proven responsibility for full design flow to design closure and tapeout.
- Knowledge of automating and advancing flows with proficiency in scripting.
- Ability to perform debug and analysis of designs, libraries, and technology files.
- Good communication and excellent collaboration skills.
This position is based in our Edinburgh office, UK.
This is a hybrid position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning employment with Cirrus Logic.
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Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role.
At Cirrus Logic, we believe that diversity drives innovation, and we are committed to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued. We aim to promote a workplace where everyone can contribute irrespective of race, colour, national origin, religion or belief, gender or gender identity, sexual orientation, age, marital status, pregnancy status, or disability.
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