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Cadence Design Systems

Sr Principal Design Engineer

Posted 10 Hours Ago
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Katowice, Śląskie
Senior level
Katowice, Śląskie
Senior level
As a Sr Principal Design Engineer, you will lead the development of complex IPs such as PCIe and Ethernet, oversee RTL design and deployment of front-end design tools, and support customer interactions while participating in technical reviews and standards bodies.
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Cadence Silicon Solutions Group (SSG) develop leading edge Silicon Solutions for a variety of High-Tech Markets. Cadence Silicon Solutions leverage decades of experience in IP and subsystems to power our customers advanced designs.

The Cadence IP Vision is to deliver industry-leading IP solutions that enable our customers to succeed in these fast-moving application spaces.

The Sr Principal Design Engineer will be based in Katowice, Poland as part of an experienced Controller IP Team with long established Controller development sites in Europe and India.

Job Responsibilities:

  • Development of complex IP such as PCIe, UCIe, CXL, Ethernet, MIPI-Visual
  • Development of RTL, Testbenches & FPGA Platforms
  • Technically leads small teams/multidiscipline
  • Deployment of Front-end design tools e.g. LINT, Synthesis and CDC Tools
  • Support customer pre-sales and post-sales meetings
  • Participate in Technical Review Meetings and Checklist Reviews as part of ISO-9001
  • Represent Cadence in Standards Body Working Groups e.g. JEDEC, IEEE, PCI-SIG, MIPI

Job Qualifications:

  • Degree in Electrical/Electronic Engineering, Microelectronics, or a related discipline
  • 12+ years’ experience in microelectronics/EDA industry
  • Proficient in Verilog coding, RTL design and complex control path and data path designs
  • Knowledge of any of the interface Protocols like ONFi, UCIe, PCIe, USB, MIPI, Ethernet
  • Experience of Metric Driven Verification (MDV) essential
  • Knowledge of RTL checks - LINT, SDC, CDC
  • Familiar with synthesis flow, LEC and timing constraints
  • Experience in writing Verilog testbench and running simulations
  • Excellent oral and written English essential
  • Self-motivated with excellent planning, interpersonal, and communication skills

Additional Skills/Preferences:

  • Experience of AMBA, PCIe, CXL & UCIe protocols preferred
  • Experience of Quality processes, such as ISO-9001 & ISO-26262 preferred

Additional Information:

Cadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace. 

Check out what we can offer you:

  • Private Health Insurance
  • 5 days Volunteering Time off each year
  • Employee Stock Purchase Plan
  • Competitive salary package adequate to competencies
  • Internet Expenses reimbursement
  • Competitive Referral Program
  • Work from the office or Hybrid Work
  • Flexible working hours
  • Life insurance
  • Multisport Plus cards
  • Social Fund benefits
  • Recommendation bonuses & Internal recognition program

We’re doing work that matters. Help us solve what others can’t.

Top Skills

Cxl
Ethernet
Mipi
Pcie
Ucie
Verilog

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