Top Design Engineer Jobs in Edinburgh

The Sr Principal Design Engineer will lead complex Silicon programs, define next generation Chiplets, integrate IP solutions, and guide technical teams. Responsibilities include quality assurance, planning activities, cross-functional meetings, and representing Cadence at conferences.

Lead digital architecture design for motor drive ICs, oversee implementation and validation, mentor engineers, and evolve methodologies.

The Electrical Design Engineer will design electrical systems for industrial machinery, collaborate on specifications, and ensure CE marking compliance, focusing on integration and documentation.

Responsible for developing low-power, high-performance ICs in advanced CMOS processes, including design, validation, and post-silicon activities.

The Senior Physical Design Engineer will implement RTL to GDS2 physical designs for ASIC projects, collaborate with design teams, and enhance methodologies.

Design mechanical systems for buildings, ensuring compliance with regulations. Perform calculations for heating, cooling, and drainage, and prepare design reports.

The Graduate Digital Design Engineer will work on digital and mixed-signal designs, develop RTL, collaborate with teams, and maintain design quality.

The Staff Digital Design Engineer is responsible for designing low-power digital circuits, managing the development lifecycle, mentoring juniors, and providing technical leadership in mixed-signal applications.

Lead technical delivery of HV/EHV cable system projects from concept to completion. Develop and validate cable designs, perform thermal, electromagnetic and mechanical modelling, advise on ratings and installation methods, coordinate multidisciplinary teams, provide client technical assurance, support procurement/construction/commissioning, undertake inspections and vendor oversight, mentor staff, and contribute to business development and technical standards.

Design and verify digital IC blocks for mixed-signal SOCs on advanced nodes. Develop RTL (Verilog/SystemVerilog), block-level testbenches, collaborate on synthesis/timing/DFT/P&R, contribute to reviews, and mentor junior engineers. Work hybrid from Edinburgh.

Lead the design, development, and verification of test solutions for products, collaborating with teams and ensuring quality. Utilize Lean Sigma principles to improve processes.

Design and develop digital circuit architectures from concept through production for mixed-signal SoCs. Create block-level RTL, verify designs, perform synthesis and timing analysis, collaborate across teams, and mentor junior engineers to ensure IP quality and delivery.

Design and develop digital circuit architectures for mixed-signal SoCs, collaborate with systems/analog/physical/verification teams, contribute to product definition, prototype evaluation, testing and product release, and participate in design reviews and project meetings.

Lead transistor-level design and verification of low-power, high-performance mixed-signal ICs (ADCs/DACs, LDOs, PLLs, op-amps, AFEs). Perform modeling, layout oversight, post-layout simulation, lab bring-up, silicon debug, validation, and production test support.

Lead and grow the centralized IP Integration Digital team; define strategy and requirements; oversee transistor-level design, characterization, Verilog modeling, Cadence-based simulation and layout; collaborate with product, foundry, and quality teams to deliver qualified digital and I/O IP on schedule.

Design and verify custom CMOS analog blocks like amplifiers and oscillators. Lead projects, mentor juniors, and ensure high-quality documentation and performance.

The Staff Package Design Engineer will create packaging solutions for high-performance products, collaborate with teams, and drive design improvements and validation processes.

Lead architecture and implementation of digital architectures for IP and full SoC designs, drive RTL development, FPGA/emulation validation, DFT/DFM application, collaborate with cross-functional teams, mentor junior engineers, and ensure first-pass silicon success.

Lead end-to-end physical implementation of major IP blocks or full-chip designs: floorplanning, place-and-route, clock tree synthesis, timing closure, physical verification, and automation of flows. Collaborate with RTL, DFT, verification, package, and library teams to meet PPA targets, mentor junior engineers, and drive manufacturability and sign-off across PVT corners.

Design analog power management circuits at transistor level, solve complex design challenges, collaborate with cross-functional teams, and mentor junior engineers.

The Principal Design Engineer will shape AI-powered product experiences, lead design discussions, collaborate with teams, and mentor designers while advancing the design system.

The Mobile UI/Design Engineer will enhance the Kraken app's UI with fluid, gesture-driven interactions in React Native, optimizing for performance and mentoring other engineers.

As a Staff Design Verification Engineer, you'll ensure the correctness of complex ASIC designs, develop verification plans, maintain testbenches, and mentor junior engineers.

Lead and execute digital verification for mixed-signal ICs: define verification plans, create reusable testbenches, drive metric-driven verification, mentor teams, and improve verification methodology.

Lead and execute digital verification for mixed-signal ICs: define verification plans, create reusable testbenches, drive metric-driven verification, coach teams, participate in methodology groups, and support hands-on RTL and gate-level debug.